The manufacturing costs of integrated circuits are largely dependent upon the chip area required to implement desired functions. The chip area, in turn, is defined by the geometries and sizes of the active components such as gate electrodes in metal-oxide-semiconductor (MOS) technology, and diffused regions such as MOS source and drain regions and bipolar emitters and base regions. These geometries and sizes are often dependent upon the photolithographic resolution available for the particular manufacturing facility. The goal of photolithography in establishing the horizontal dimensions of the various devices and circuits is to create a pattern which meets design requirements as well as to correctly align the circuit pattern on the surface of the wafer. As line widths shrink smaller and smaller in submicron photolithography, the process to print lines and contact holes in photoresist becomes increasingly more difficult.
With circuit advancement to the very-large-scale integration (VLSI) levels, more and more layers are added to the surface of the wafer. These additional layers in turn create more steps on the wafer surface. The resolution of small image sizes in photolithography thus becomes more difficult over the additional steps due to light reflection and the thinning of the photoresists over the steps. Planarization techniques are generally incorporated to offset the effects of a varied topography.
Many different planarization techniques have been used in the past, each with its own disadvantages. Multilayer photoresist processes have been used to create the desired images. The particular photoresist process depends upon the severity of the topography and the size of the desired images. These processes however, take longer and require more yield-limiting steps. Polyimides and reflow glass layers are used to planarize the surface of the wafer. Polyimides can be spun onto the wafer like the photoresist materials. After application, the polyimide is covered with a hard layer and patterned like the photoresists. Reflow glass layers are generally doped with boron or phosphorous or both to lower the temperature at which the glass layer will flow. While these layers achieve more planarization than previous methods, additional planarization is still required as the device geometries continue to shrink.
Spin-on-glass (SOG) is also a hard planarizing layer which is a mixture of silicon dioxide in a solvent that quickly evaporates. There may be carbon in the SOG to reduce the SOG's susceptibility to cracking after it is baked. SOG, by itself, however, is unable to prevent mobile ionic contaminants from travelling through the layer and into the devices or wafer surface below the SOG.
It is therefore an object of this invention to provide a method of forming a planarizing layer which is capable of preventing mobile ionic contaminants from traveling through the planarizing layer and into the underlying layers.
It is a further object of this invention to provide such a method which utilizes a doped spin-on-glass insulating layer.
It is a further object of this invention to provide such a method which utilizes conventional process flows.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.